The following patent applications, assigned to the same assignee hereof and filed on even date herewith in the names of the same inventors as the present application, disclose related subject matter, with the subject of each being incorporated by reference herein in its entirety:
Memory Module with Hierarchical Functionality, Attorney Docket No. 40050/B600/JFO; High Precision Delay Measurement Circuit, Attorney Docket No. 37079/B600/JFO; Single-Ended Sense Amplifier with Sample-and-Hold Reference, Attorney Docket No. 37362/B600/JFO; Limited Switch Driver Circuit, Attorney Docket No. 37361/B600/JFO; Fast Decoder with Asynchronous Reset with Row Redundancy; Attorney Docket No. 37115/B600/JFO; Diffusion Replica Delay Circuit, Attorney Docket No. 37360/B600/JFO; Sense Amplifier with Offset Cancellation and Charge-Share Limited Swing Drivers, Attorney Docket No. 37363/B600/JFO; Memory Architecture with Single-Port Cell and Dual-Port (Read and Write) Functionality, Attorney Docket No. 37364/B600/JFO; Memory Redundancy Implementation, Attorney Docket No. 37496/B600/JFO; and; A Circuit Technique for High Speed Low Power Data Transfer Bus, Attorney Docket No. 37497/B600/JFO.
1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like.
The present invention satisfies the above needs by providing in a memory module having memory cell groups, a decoder having a synchronous portion, which receives and responds to a clocked signal; an asynchronous portion which is coupled with an asynchronous circuit in a selected memory cell group of the module; and a feedback-resetting portion, coupled with, and interposed between the synchronous portion and the asynchronous portion, which substantially isolates the synchronous portion from the asynchronous portion in response to a predetermined asynchronous reset signal, which can be a monitor signal from a monitor node. Also, the decoder can include an inverter and multiple buffer stages, which can be skewed relative to each other, so that load capacitance is thereby reduced. The decoder can be a row decoder, disposed to be a asynchronously-resettable row decoder, as well as a column decoder, disposed to be an asynchronously-resettable column decoder.
In another embodiment according to the present invention, a decoder can have a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. The selector can include a multiplexer which selects between the first and second memory cell groups. Typically, the decoder decodes the first memory cell group. However, in response to a group-select signal, the decoder also can select and decode the second memory cell group. The memory cell groups can be adjacent memory cells within the memory module, or an assigned memory cell and a redundant memory cell. This decoder is suitable for employing as a row decoder, where the memory cell groups are memory rows, as well as a column decoder, where the memory cell groups are memory columns.
Furthermore, in another embodiment of the present invention, a decoder can combine the features and functionality of the aforementioned decoders to provide an asynchronously-resettable decoder with redundancy. Such a decoder can have a synchronous portion, which receives and responds to a clocked signal; an asynchronous portion which is coupled with an asynchronous circuit in a selected memory cell group of the module; a feedback-resetting portion, coupled with, and interposed between the synchronous portion and the asynchronous portion, which substantially isolates the synchronous portion from the asynchronous portion in response to a predetermined asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the following drawings.